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Frontline of Semiconductore Design with EDA Vendor 

Thursday, December 12 | 12:30 pm - 2:10 pm

TechSTAGE SAKURA  East Hall 7

Free  Interpretation via Smartphone
EARPHONE NEEDED to listen to the interpretation audio from your own smartphone.

Each EDA vendor will engage in heated discussions about future design and verification across vendor boundaries. The current state of semiconductor circuit design, packaging, and system-level design and verification for chiplet use will be reviewed, issues will be identified, and future directions will be discussed.

Program Agenda
*Please note that the program may be subject to change.

12:30 - 14:10
Panel discussion

 

Panelist

Kazuhiro Kariya
Kazuhiro Kariya
Senior Managing Executive Officer, CTO
Zuken
Kazuyuki Yorogo
Kazuyuki Yorogo
Technical Director
Field Application Engineering
Siemens EDA Japan
Kazunari Koga
Kazunari Koga
Principal Engineer
EDAG
Synopsys
Tadaaki Hitomi
Tadaaki Hitomi
AE Manager
Custom IC & Simulation & SPB
Cadence Design Systems
Keitaro Otsuka
Keitaro Otsuka
Manager
Application Engineering
MathWorks Japan 
Bill Baker
Bill Baker
Director
Asia Semiconductor Sales  
Ansys 

Moderator

Nobuaki Kawahara
Nobuaki Kawahara
Executive Director
ASRA
Mitsuya Ishida
Mitsuya Ishida
Director
3D Assembly Planning Department
Rapidus

Stage Sponsors