STS Advanced Lithography Session
Lithographic Divergence from 2D Scaling to 3D Applications
Conference Tower 607 / Online (Zoom)
Fee (Exclusive of tax)
- Per Session : SEMI Members 10,000JPY / Non-Members 20,000JPY
- STS 1 Day Pass : SEMI Members 27,000JPY / Non-Members 54,000JPY
*Above fee includes "Download Presentation Materials" (some presentation materials might be written in Japanese)
*Please note that there are separate tickets for in-person and online participation.
High NA EUVL has finally begun to be introduced to cutting edge area. Alternative technologies of NIL and DSA are also steadily moving towards practical use and are being evaluated by users. On the other hand, lithography is also required in vertical integration called 3D scaling for advanced packages and bonded wafers.
< SEMI Technology Symposium (STS) >
This first technology seminar series in SEMICON Japan founded in 1982, now grown to the international tech symposium marks the 43rd this year. It has been developed as a place to discuss technology among engineers by picking-up the semiconductor technology trends and its issue and sharing the practical technologies to the industry. This symposium stimulates global business growth by involving a variety of different players and visitors.
This program is organized thanks to "SEMI Technology Steering Committee (STS)" formed by top engineers from industry-leading companies, universities, and research institutions.
Program Agenda
*Please note that the program may be subject to change.
Session Chairs: *In alphabetical order by company name
Seiji Nagahara (ASML Japan), Keita Sakai (Canon), Hajime Aoyama (NIKON)
Cost-effective scaling of device density is continuing with the advanced lithography. This presentation will cover the current status and future outlook of Extreme Ultraviolet (EUV) lithography using 0.33 numerical aperture (NA) manufacturing tools and next-generation 0.55 NA (High-NA) tools. We will also discuss key innovations in metrology and computational lithography for maximizing the capabilities of EUV exposure tools.
The multi-patterning technologies with ArF immersion lithography are fully utilized for the latest DRAM mass production. Also, the latest EUV technology has been started to be applied. On the other hand, alternative patterning technologies such as DSA and NIL are under development due to high cost of EUV. In this presentation, I will talk about patterning strategy for next generation DRAM.
In addition to the miniaturization of semiconductor devices through the adoption of EUV, the More-than-Moore approach, which realizes the sophistication of semiconductors without miniaturization, is one of today's hot topics.
Advanced packaging is a technology that improves computing power by interconnecting a system-on-a-chip (SoC) and memory in packages.
In this presentation, we discuss patterning technology for advanced packaging.
In recent years, the necessity and importance of wafer bonding technology has been increasing in advanced devices, and it is now expanding not only to CIS but also to Logic, NAND, and DRAM such as BSPDN, Memory-cell and CMOS circuit stacking and more. In this presentation, we will introduce the importance and challenges of wafer bonding technology, and solutions to wafer distortion error caused by wafer bonding.