STS Testing Session
Test Technology in the Chiplet Devices
Conference Tower 607 / Online (Zoom)
Fee (Exclusive of tax)
- Per Session : SEMI Members 10,000JPY / Non-Members 20,000JPY
- STS 1 Day Pass : SEMI Members 27,000JPY / Non-Members 54,000JPY
*Above fee includes "Download Presentation Materials" (some presentation materials might be written in Japanese)
*Please note that there are separate tickets for in-person and online participation.
Today's semiconductors tests are increasingingly using chiplets that utilize packaging techonology. It is necessary to test groups of complexly configured chips without compromising quality. We will provide a forum for discussion and have cutting-edge researchers give talks on these testing technologies.
< SEMI Technology Symposium (STS) >
This first technology seminar series in SEMICON Japan founded in 1982, now grown to the international tech symposium marks the 43rd this year. It has been developed as a place to discuss technology among engineers by picking-up the semiconductor technology trends and its issue and sharing the practical technologies to the industry. This symposium stimulates global business growth by involving a variety of different players and visitors.
This program is organized thanks to "SEMI Technology Steering Committee (STS)" formed by top engineers from industry-leading companies, universities, and research institutions.
Program Agenda
*Please note that the program may be subject to change.
Session Chairs: *In alphabetical order by company name
Rocky Kobayashi (ATE Service), Hidenori Akiyama (Nuvoton Technology Corporation Japan)
In recent years, chiplet technology, which mounts logic semiconductors, memory and other components on a single substrate, along with miniaturisation, has been attracting attention as a means of achieving higher performance semiconductors. Renesas SOC's latest product range is also developing a market strategy based on chiplet technology. In testing chiplet products for automotive semiconductors, testing of individual semiconductor chips and testing in a packaged state is required, and there are issues such as the connection between chips and the heat generated during operation, and optimal test technologies that take mass production into consideration are being investigated to address these issues. This presentation introduces these efforts.
We would like to discuss the dynamic and rapidly evolving landscape of the global semiconductor wafer testing market. As we will explore the latest advancements in the Testing challenges of future of chiplets, HPC and HBM.
The global semiconductor wafer testing market is on the cusp of significant advancements. By addressing the challenges associated with advanced packaging, chiplets, HPC, and HBM, we can unlock new levels of performance and efficiency. Look forward to exploring these topics in greater detail and discussing how we can collectively shape the future of the semiconductor industry.
TBA
Currently, the development of power devices such as SiC and GaN are accelerating due to demands from the automotive and the industrial markets. In addition, in order to maximize its performance, GaN and driver IC are integrated in SiP. Especially, the slew rate of GaN is fast, so testing of less than 1 ns is required. Therefore, a Sub-ns testing technique for mass production was developed. In my presentation, its principle and experimental results are shown.
Session Sponsor
