Overview of Back-End Processes for Young Engineers II
A Must-Have for Young Semiconductor Engineers! Seminar on the Latest Packaging Technology that Supports Next-Generation Semiconductors
Conference Tower 606
*JAPANESE ONLY PROGRAM
Fee (Exclusive of tax) :
- Per Session SEMI Members 20,000JPY / Non-Members 40,000JPY
- 1 Day Pass SEMI Members 25,000JPY / Non-Members 50,000JPY [Overview of Back-end Processes for Young Engineers I / II]
*Above Fee Includes
- Right to attend the APCS/ADIS Networking Party on 12/12(Wed.) *Students are Not Allowed
- Luch box for applicants of 1 day pass
**Presentation Materials will not be distributed.
This two-part session will cover semiconductor packaging technology, which holds the key to the future evolution and development of semiconductors, in a wide range of topics.
In this afternoon session, you will learn about the latest trends in semiconductor post-processing and packaging technology, as well as the latest technologies such as 2.5 and 3D mounting, chiplets, and hybrid bonding.
In addition, those attending this session will be able to participate in the APCS/ADIS networking event (12/12) where you can interact with key people in advanced packaging technology.
*As this event will serve alcohol, students are not permitted to attend.
Program Agenda
*Please note that the program may be subject to change.
This seminar outlines the three key technologies of the latest advanced microelectronic packaging: interposers, hybrid bonding, and backside power delivery network (BSPDN). The key driver is "Chiplets" such as xPU and HBM that are split from a large SoC and designed to be efficiently interconnected using 2.xD architecture to achieve high performance and functionality. In addition, 3D-IC/TSV and Chip-to-Wafer integration technologies are described.
概要：TBA