Semiconductor Process Technology 2Days
Intensive Lectures on Diffusion/Implantation, Lithography, Etching, and Multilayer Interconnect Manufacturing Processes
Conference Tower 605
*JAPANESE ONLY PROGRAM
Fee (Exclusive of tax) :
SEMI Members 46,000JPY / Non-Members 67,000JPY
*Applies whole two-day program holding on Dec.12 -13.
*Includes "Semiconductor Process Textbook" and "Lunch Box"
This very popular educational seminar covers the fundamental to the updated manufacturing process of Diffusion/ Implantation, Lithography, Etching, Multilevel Interconnect by each technical experts with various charts and tables. In addition to this, Power Electronics has also been added to the program to provide more comprehensive content.
*This program is provided only in Japanese.
Program Agenda
*Please note that the program may be subject to change.
Day 1
Among various process technologies used for silicon semiconductor device fabrication, fundamentals are comprehensively explained regarding oxidation, diffusion, ion implantation, annealing and LPCVD with their based model. Furthermore, examples of equipment and devices are shown where those process technologies are applied in practice.
Fundamental lithography technologies such as exposure, illumination methods, mask, resist and resist processes will be presented. About resist I'll explain dissolution inhibition resist and chemically amplified resist. The talk of advanced lithography technologies (immersion lithography, double/multiple patterning, EUV lithography, directed self-assembly (DSA) lithography, nanoimprint) will be given along the latest roadmap.
Day 2
The principles of dry etching technology used for processing and surface treatment of various materials, control of active species in plasma and ion energy control on the substrate surface will be explained. Various plasma systems and processes for materials such as Si, SiO2, SiOCH, etc. will also be reviewed.
For the comprehensive understanding of power devices, I explain the required functions, the corresponding basic operations, and the historical development process of these. Then, I explain the current major power devices such as structures, electrical characteristics, and their advantages and disadvantages. Finally, I introduce new devices for the next generation and their expected performances.
Aluminum multilevel interconnect technology is explained by focusing on its necessity, interconnect structure and constituent materials such as metal and dielectric film. CMP, which plays an important role as an interlayer planarization process, is also discussed. In addition, Copper/Low-k multilevel interconnect technology, which is increasingly being applied to advanced semiconductor devices, is explained by focusing on its necessity, process issues and measures.