Proposals to the Assembly Technologies to Drive 3D-IC
Friday, December 6
TechSTAGE WEST, Hall 1, Makuhari Messe
TechSTAGE WEST, Hall 1, Makuhari Messe
The deployment to various applications of the required packaging technology to accelerate the commercialization of 3D-IC technology will be proposed by the leading companies of Equipment & Materials manufacturers.
Haruo Shimamoto, TF Leader, SEMI Standards Japan Packaging Committee
3D-IC TSV Standard Activities under SEMI
SEMI has been working on 3D-IC TSV standard activities at North America, Taiwan and Japan region. The area for the task force team working are to define and specify the manufacturing processes, inspection/measurement and materials properties. Several documents are published as SEMI standard. In this speech, overall of standard activities and standard specifications are introduced to promote the audiences to use the 3D-IC TSV techniques.
Market and Technology Trends for 2.5/3D and Wafer Level Packaging
President Japan Office
Wafer level packaging market is started to gain more and more significance in the semiconductor industry, showing a great potential for future growth. By 2017, 23% of the total IC semiconductor industry will be manufactured using packaging technologies, such as bumping, redistribution, through silicon vias, etc. If historically, the wafer level packaging was mostly supported by flip-chip wafer bumping, today the industry is benefiting from a large variety of different packaging technologies and platforms, including 3D IC stacking. It is a real opportunity for the entire supply chain to work together and further consolidate and strengthen the system value-chain in order to fully take advantage of the benefits and advantages 3D IC can bring. In this presentation, Yole Développement will look at the current status of the 3D Packaging industry, provide the technical and market trends for 2.5 & 3D stacking technologies, highlighting the driving applications and their expected evolution.
Development of Temporary Bonding Solution for 3D TSV, with Simple Room Temperature de-bonding process
Japan and ASEAN Manager, Application Engineering
Dow Corning Toray
Temporary Bonding materials/processes are identified as the key building blocks for 3D TSV, but this process is one of the biggest items preventing high volume manufacturing due to its complex process and high CoO. Temporary Bonding Solution is under development to help remove limitations of existing materials/processes; by providing a simple spin coated, room temperature mechanical de-bonding solution. We will provide update of such development status.
Suggestions as an Assembly Equipment supplier for 3D-IC packaging
Assistant General Manager, Engineering Division
3D-IC packaging for consumer products is in a transition period to high volume manufacturing. Some of technology driver products in IDMs and OSATs are being expanded the production capacity to gain market share. It has become an unavoidable technology to maximize electrical performance of high functionality of latest silicon wafer and to expedite the product differentiation. However, there are some issues to be solved in order to be a main stream packaging technology. In those, packaging cost is one of major issue and this is discussed commonly enough before use of a new technology is going to be an explosive increase. In this session, ideal state of equipment and packaging materials are discussed to reduce the cost and some of ideas are suggested figuring out a path to main stream packaging technology.
Undefill Matrial & Liquid Molding compound for the 2.5D, 3D Package
Engineer, Electronics Materials Development Division Packaging Materials Section
Nagase ChemteX Corporation
New Under fill & Over mold materials are actively developing for 2.5D-3D package. Wafer level under fill are developing for fine configuration. And also, LMC(Liquid Mold Material) is expected as over mold material. These materials were need not only reliability but also processability for new process. This paper was reported the expected features for these materials.
Latest wafer bonders which drive 3D-IC technology
Head of Technology Japan / Applications Engineer, Technology Division
EV Group Japan
Wafer bonders are indispensable in 3D-IC and TSV manufacturing. Nowadays, we can see many 3D-IC products in not only niche market but also consumer market, where wafer bonders are used in manufacturing. Technical requirements, current performance, and future roadmap will be presented in the talk. The recent progress of TB/DB technology as well as importance of Japan’s role in 3D-IC area will be also explained.
Transport challenges of 3D device and thin die
Manager, Production Engineering Department, Technology Development Headquarters
The Chipping and Contamination is the issue of thin chip and thin wafer shipping .
The Increasing of 3D , 2.5D devices needs to improve the safety in shipping.
We'll report the results of some experiments, the shock , picking up and the influence on devices with Chip tray and Adhesive trays.
Content & Summary of this Semminar
Haruo ShimamotoTF Leader, SEMI Standards Japan Packaging Committee
To acceralate the practical use of 3D-IC, SEMI standard packaging committee wants to announce about packaging elemental technologies are ready for massproduction. New suggestions of materials and equipments used in 3D-IC assembly process except for TSV fabrication are reported from distiguished companies in this industry. And finally, I report the summary about the future problem.
Proposals to the Assembly Technologies to Drive 3D-IC:
Free of charge (Registration required)
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TechSTAGE's seminars presentation materials:
JPY 5,000 (consumption tax not included)
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