SEMI is soliciting papers from authors around the world for SEMI Technology Symposium 2012 (STS 2012) at SEMICON Japan 2012, which takes place December 5-7 at the Makuhari Messse in Chiba, Japan.

Submission Deadline:　June 8, 2012
Submit to: 　jprogram@semi.org
*You will be notified status of your submission by the end of July.

Guidelines 

- Submit a 150 word abstract and a 100-word speaker biography

- Accuracy in Title and Description: The quality of the description of your presentation matters. The ability for your description to clearly explain what the attendees will take away from your presentation is critical for your submission to make it through the review process.

- Abstracts must clearly detail the nature, scope, content, organization, key points and significance of the proposed paper. Presentations are to be original and non-commercial in that they focus on the technical merits of a process rather than on the individual company's product benefits.

Topics

Lithography

• Optical Steppers/Scanners (Dry & Wet)

• EUV Scanner

• Image Evaluation Technology

• Aberration

• Overlay

• Focusing

• Resolution Enhancement Technology

• Photo resist

• Light Source Development

• Next generation patterning technologies-EB/Nanoimprint/DSA/others

• Metrology

• Lithography Simulation Technology

• Double/Multiple patterning

• Computational Lithography

DFM &Mask

• DFM Technology

• Design and Process Integration

• OPC, PPC, RET Mask Data Processing

• ORC, Process Modeling, Mask Printability Simulation

• PSM and CPL

• EUV Masks

• Metrology

• Defect Inspection/Repair

• Cleaning/ Pellicle/ Haze Control

• Process Control

• Template technologies for Nanoimprint

• Mask writing technologies

• Mask handling technology

Inspection / Metrology

• CD measurement

• Pattern profile measurement

• Hot spot inspection

• Film thickness measurement

• Integrated Metrology

• Virtual Metrology

• Particle, defect inspection

• Defect review, analysis

• Yield Management

• Electrical property testing

• TEG

Advanced Device Technology / Process

< High performance device technology (More Moore) >

•            Advanced logic device

•            Advanced memory device

•            Analog, passive device

•            Power device

•            Emerging research device( post CMOS, post Flash/DRAM)

< IC multiple functional technology (More Than Moore) >

•            On-chip embedded IC technology (System On Chip)

•            3D embedded IC packaging technology (System in Package)

•            IC interconnect technology (Through Si Via, nano-optical/wireless connection)

•            Si logic device embedded

with memory/analog/passive/power device,

with heterogeneous device,

with MEMS,

with bio chip,

with organic device,

with electroluminescence device,

with power generation device.

<Advanced Devices Process >

Packaging

<New　Product>

• LED

• Sensor

• Wreless　Module

• Poweｒ　Device

• MEMS　Produt

 <New　Technology>

• SiP

• Flip Chip

• Assembly Technology in Ultra High Speed

• Environmental Assembly Technology (Lead free, Eco-design)

• 3D Packaging/TSV etc.

• Wafer Level Packaging

• Thermal, Electrical Design 

• Multi-bus(Wide I/O), connection, Micro-Bump

• Printed Technology

Testing

• DFT, DFM, DFA, DFR

• Cost of testing

• Analysis technology

• Measuring methods

• Peripheral technology, such as Probe/Contact

• Others

Microsystems/MEMS

• Microsystem

• Micro Electro Mechanical Systems (MEMS)

• Micromachining

• Nanomachining

• 3D microfabrication

• Equipments for fabrication and testing

• Micro sensors

• Micro actuators

• Micro structures

• Micro energy sources

• Packaging

• Integrated MEMS

• MEMS foundary

• Domestic and oversee circumstance

For more information, contact Nobuko Yamamoto at jprogram@semi.org