Advanced Wafer Geometry vs. Lithography Workshop 

 

  • International Advanced Wafer Geometry Task Force is one the oldest Task Forces of SEMI Standards Technical Committees and has developed a lot of SEMI Standards for wafer geometry at time to time.

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    At SEMICON Japan 2011, the International Advanced Wafer Geometry Task Force plans to have open workshop to share the updated information for next generation wafer characteristics.

     

     

    Chair:

     

    Masanori Yoshise, KLA Tencor 
    Satoshi Akiyama, Raytex

     

    Date:

     

    Thursday, December 8

     

    Time:

     

    09:30-11:45

     

    Location:

     

    Room 303, International Conference Hall, Makuhari Messe

     

    Fee:

     

    Free 

    Translation:

     

    No Interpretation

     

    Register:

     

    register

     

     

    アジェンダ 

    09:30 

    Opening Remarks 

    09:40

    Incoming Metrology Challenges on UTSOI using WS2 AMP 
    Chistophe Maleville, SOITEC

    Challenges and strategy of controlling incoming material for better UTSOI yield is studied. Relationship between wafer geometry and defectivity is studied in this development activity. 

    10:10

    Wafer Geometry and Lithography Focus Performance for Advanced Nodes 
    Ralph Brinkhof, ASML

    Wafer geometry rodadmap is driven by shrinking Lithography Depth of Focus (DoF). Only 15% of DoF budget allotted for flatness for EUV. Edge Roll Off metrics directly relates to near edge defocus. Localized features on front and back surface of the wafer impacts lithography defocus.
    (Update of SEMICON West presentation)

    10:40

    Localized Geometry Characterization and Rethinking Wafer Shape Concept
    Jaydeep Sinha, KLA Tencor, on behalf of Joann Qui, Intel

    Wafer geometry has been expanded from flatness to NT in 1999, to ERO in 2004 and to Edge Dimensions in 2006 and now to localized feature characterization for various IC applications. Traditional metrics are insufficient or non-optimal to detect and characterize these localized features of interest including complex contours of wafer shape. Understanding the interaction of these features with different IC processes and their impact to yield needs more understanding.
    (From SEMICON West presentation)

    11:10

    What do the lithography tools recognize the surface of wafers?
    Hiroshi Nomura, Toshiba

    A professor said, what measurable can be improved and what immeasurable cannot. His student developed sub-nanometer focus metrology with a special mask to prolong this optical lithography era. Now we can easily have what the lithography tools recognize the surface of waters.
    (From JSAP March 2011, conducted in Japanese)

    11:40

    Wrap-up and Closing Remarks

     

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